Basic Info.
Model NO.
LAP-C16032, LAP-C16064, LAP-C16128, LAP-C162000
Product Description
Logic Analyzer,LAP-C162000,LAP-C16128,LAP-C16064,LAP-C16032,digital circuits development, test, analysis and debug, Free more than 100 Protocols:
Automotive
CAN 2.0B,CAN FD,DSI Bus,FlexRay 2.1A
LIN 2.1,MVB,SENT,WTB
PC System
AMD_SVI2,DDC EDID,eSPI,FWH
GPIB,IDE Low Pin Count,LPC-SERIRQ
LPT,PCI,PECI,PS/2
Serial GPIO IBPI,SVID,USB 1.1,USB 2.0
IC Interface
1-WIRE,1-Wire(Advanced),3-WIRE,BDM
HPI,I2C,I3C,JTAG 2.0
MICROWIRE,MCU-51 DECODE,MDDI,SPI
SSI Interface,ST7669,SLE4442,SPI PLUS
Serial Wire Debug(SWD),UART(RS-232C/422/485)
Digital Audio
AC97,AES_EBU,DSA Interface,DP AUX Channel 1.1
HD Audio HDMI CEC,I2S,MIPI DSI
MHL-CBUS,MIDI,MIPI_CSI-2 PCM
PSB Interface,S/PDIF,STBus
Basic Logic Application
ARITHMETICAL LOGIC,DIGITAL LOGIC,JK FLIP-FLOP,UP DOWN COUNTER
Memory
Compact Flash 4.1,eMMC,I2C(EEPROM 24L),I2C(EEPROM 24LCS61/24LCS62)
MICROWIRE(EEPROM 93C),Quad SPI,SPI Compatible(Atmel Memory),SAMSUNG K9(NAND Flash)
SD2.0/SDIO,SD3.0,UNI/O
Optoelectronics
7-SEGMENT LED,CCIR656,CMOS IMAGE,DALI Interface
DM114/DM115,DMX512,LCD1602,LCD12864,SCCB
LED Pitch Array,LG4572,RGB Interface,S2Cwire/AS2Cwire
Infrared rays
IRDA,NEC PD6122,Philips RC-5,Philips RC-6,PT2262/PT2272
Power
BMS,HDQ,PMBus 1.1,QI,SMBus 2.0
Wireless
Differential Manchester,DigRF,ISO7816 UART,KEELOQ Code Hopping
MANCHESTER,MII,MILLER,MIL-STD-1553
MIPI RFFE MODIFIED MILLER,SIGNIA 6210,SWP
WIEGAND WWV/WWVH/WWVB
Other
DS1302,DS18B20,HART,IO-Link
KNX,Line Code,ModBus,MODIFIED SPI
OPENTHERM 2.2,PROFIBUS,SHT11,YK-5
Logic Analyzer,LAP-C162000,LAP-C16128,LAP-C16064,LAP-C16032,digital circuits development, test, analysis and debug Specifications
Sampling Frequency:Internal Clock (Timing) (Asynchronous): 100Hz~200MHz External Clock (State) (Synchronous): 100MHz
Channel:16ch
LAP-C162000,Memory Depth per Channel 2Mbits,total memory 32Mbits (Max 512Mbits for compression)
LAP-C16128,Memory Depth per Channel 128Kbits,total memory 2Mbits;
LAP-C16064,Memory Depth per Channel 64Kbits,total memory 1Mbits;
LAP-C16032,Memory Depth per Channel 32Kbits,total memory 512Kbits.
Test Signal:Bandwidth 75MHz
Range of the Trigger Voltage: -6V~+6V
Resolution of the Trigger Voltage: ±0.1V
Others:System Support: Windows 2000 / XP(32bits) / Vista / Win 7
Error in Phase: < 1.5ns
Max. Input Voltage: ±30V
Input Resistance: 500KΩ/10pF
Power Supply: USB (DC 5V, 500mA)
Power Consumption at Rest: 1W
Max. Instant Power at Work: 2W
Software Function:Data Compression : Max 2M bits x 256
Time Base Range : 5ps~10Ms
Languages: Chinese (Traditional/Simplified), English, Japanese, Korean, French, German
Maximum Trigger Page : 8192 Pages Waveforrm Data Display Filter&Filter Delay Trigger Delay Unlimited lncreasing Bar Automatic Attaching Bar Automatic Software Upgrade Data Statistic Auto-Save Filter Bar Protocol Analysis Protocol Packet List File Export Data Contrast Latch Function Protocol Analyzer Trigger: parallel Pulse Width
Trigger Module : option
Trigger Mode: Pattern/Edge
Trigger Channel: 16 CH
Post-Trigger: YES
Trigger Level: 1 Level
Trigger Count: 1~65535
Safety Certification: FCC / CE / WEEE / RoHS / REACH
Dimensions:125 x 92 x 25 mmFeature
The Buttons on the Logic Analyzer Hardware Own the Function of Sampling.
There is a START button on the hardware of Zeroplus Logic Analyzer, and pressing this button can make the Logic Analyzer sample signals when the software of Logic Analyzer is activated. Users can quickly capture data from the testing board by using the START button.
Compression
Zeroplus Technology issues the patent technology of Waveform Compression which can capture more waveform data without adding the size of the RAM. For example: The RAM Size is set as 1M, and the Sampling Frequency is set as 50MHz. When the Compression function is not activated, Zeroplus Logic Analyzer can only capture waveform data within 20.972ms; when the Compression function is activated, with the same RAM Size (1M) and Sampling Frequency (50MHz), the Logic Analyzer can prolong the waveform data to 3.999s. That is to say, the function of Waveform Compression can improve the amount of the captive data largely.
Signal Filter Delay
Zeroplus Technology issues the patent technology of Signal Filter Delay. The function of the Signal Filter Delay can capture the signals conditionally. For example, the Filter Condition of Channel A1 is set as High Level; the differences can be seen obviously by the horizontal windows. And the Filter Delay Setup can make the conditions of the Signal Filter more flexible; users can set the time of the Filter Delay as their requirements. For example: Clients found Bugs in a group of DUT. The content of the Bug is that a read error may be presented while the program tries to read the data. At that moment, users can use the function of the Signal Filter Delay to capture signal conditionally and analyze the Bug further (the Status of the Read is 0X5A; the Command Period of the Read is 10us). According to the function of the Signal Filter Delay, Zeroplus Logic Analyzer can only capture the 10us Command Period to analyze the Bug when the Data of 0X5A is presented.
Trigger Page
Zeroplus Logic Analyzer adds the patent technology of Trigger Page, in other words, the Trigger Page is to page the continuous and long signal data. Set the present RAM Size as one page, and the position of the trigger point is the first page. After analyzing the data of the first page, users can set the Trigger Page as "2" and restart the Logic Analyzer when the data of the testing board are the same for each time and the setting of the trigger condition is not to be changed; when the Logic Analyzer stops capturing the data and completes the display, the content of the Waveform Display Area is the data of the second page which follows the data of the first page. For example: The RAM Size is set as 32K; the Sampling Frequency is set as 200MHz; the Trigger Page is set as "1". The end point of the captured signal is 147.465us and the former half part of the data is 0X47. When starting to capture data with the same RAM Size and Sampling Frequency and setting the Trigger Page as "2", the start point of the captured data is 147.465us which is the end point of the first page, and users can see the latter part of the data, 0X47.
Trigger Count
Zeroplus Logic Analyzer adds the technology of Trigger Count. The Trigger Count function is suitable for this kind of tested signals which have more than one trigger signal according with the Trigger Condition. Users can decide the trigger position where the trigger signal accords with the Trigger Condition. When users want to trigger at the first time when the trigger signal accords with the Trigger Condition, the setting of Trigger Count should be "1" (it is the default); when users want to trigger at the third time when the trigger signal accords with the Trigger Condition, the setting of the Trigger Count should be "3"; the others can follow the former method. The Max. Trigger Count can be set as "65535".
Find Pulse Width
Zeroplus Logic Analyzer adds the function of Find Pulse Width which can compare and search the pulse width. For instance, the period of some waveform is 4.2us (the positive/ negative period is 2.1us respectively), but it can cause the period error sometimes; at that moment, users can use the function of Find Pulse Width to mark the error point, and it improves the efficiency for engineers to complete the Debug.
Decoding Example of Protocol Analyzer - The Decoding of Protocol Analyzer SSI
The Protocol Analyzer SSI Decoding Module of Zeroplus Technology can help users to analyze the Protocol Analyzer SSI. The data of the RD/TD in signals can be directly displayed on the screen according to the Decoding Module. The Protocol Analyzer SSI Decoding Module of Zeroplus Technology provides different SSI settings, such as Normal Mode and Network Mode. Users can set it as their requirements when analyzing the SSI Signal.
Support LabVIEW
LabVIEW for LAP-C(162000) Download How to perform logic analyzer measurement on LabVIEW
How It Works
Actual Measurement of Protocol Analyzer SSI
Step 1:Plug the testing cable into the signal connectors of the Logic Analyzer, and connect the other ends of the testing cable to the testing board; users can use the probe in the package to connect with the testing board according to the different conditions of the testing board.
Step 2:Set the conditions of the Logic Analyzer according to Chapter 3 of the Installation Guide. After completing the settings, activate the Logic Analyzer's software to send out the signal of the testing board, then the signals can be captured; the captured signal can refer to the waveform image. Tip: The Sampling Frequency of the Logic Analyzer should be more than four times higher than that of the testing board to make sure that the signal is accurate.
Step 3:Group the unanalyzed channels into Bus: press the CTRL key on the keyboard continuously, and use the mouse to click the unanalyzed channels to highlight them; when the selection is completed, click the Right Key on the mouse to select the option, Group into Bus; there will be a Bus added in the Bus/Signal column. Tip: When analyzing the Bus, set the number of channels according to the tested Protocol Analyzer. For instance, the Protocol Analyzer IIC needs two channels to start the analysis, and the Protocol Analyzer UART needs one channel to start the analysis.
Step 4:Select Bus1, and press the Right Key on the mouse; click Bus Property to open the Bus Property dialog box, and then select the desired Protocol Analyzer. There is a corresponding Parameters Configuration setting for each Protocol Analyzer; users can set the relative contents of the Protocol Analyzer in the Parameters Configuration dialog box according to the tested Protocol Analyzer. Tip: The Protocol Analyzer SPI Decoding Module of Zeroplus Logic Analyzer can analyze the MOSI and MISO synchronously, and only two groups of Protocol Analyzer SPI needs to be set to start analyzing.
Step 5:When the setting is completed, the packet data of the Protocol Analyzer SSI will be displayed on the screen. Tip: The software of Zeroplus Logic Analyzer owns other powerful functions to help users to analyze the Bus, such as Packet List, Find Data Value, Find Pulse Width, and so on.
Accessories
Logic Analyzer:1piece
Testing Cable/Probe:1packet
USB Cable:1piece
Carrying Bag:1pieceIf you are looking for higher-speed digital signals test, analysis and debug, you can refer to other products:ZEROPLUS F-standard LAP-F164256M Logic Analyzer:64 channel,Internal (Timing)(Asynchronous) max. 1GHz ,External (State)(Synchronous) max. 200MHz,Memory depth per 256Mb,Total Memory 16Gb.
ZEROPLUS logic cube pro LAP-C PRO32256M Logic Analyzer:32 channel,Internal (Timing)(Asynchronous) max. 2GHz ,External (State)(Synchronous) max. 250MHz,Memory depth per 256Mb,Total Memory 8Gb.
ZEROPLUS logic cube pro LAP-C PRO32128M Logic Analyzer:32 channel,Internal (Timing)(Asynchronous) max. 2GHz,External (State)(Synchronous) max. 250MHz,Memory depth per 128Mb,Total Memory 4Gb.
ZEROPLUS logic cube pro LAP-C PRO32064M Logic Analyzer:32 channel,Internal (Timing)(Asynchronous) max. 2GHz ,External (State)(Synchronous) max. 250MHz,Memory depth per 64Mb,Total Memory 2Gb.
ZEROPLUS logic cube pro LAP-C PRO16064M Logic Analyzer:16 channel,Internal (Timing)(Asynchronous) max. 1GHz ,External (State)(Synchronous) max. 250MHz,Memory depth per 64Mb,Total Memory 1Gb.
Address:
No. 555, Lianming Road, Hongqiao Cbd, Shanghai, China
Business Type:
Manufacturer/Factory, Trading Company
Business Range:
Auto, Motorcycle Parts & Accessories, Electrical & Electronics, Industrial Equipment & Components, Instruments & Meters, Manufacturing & Processing Machinery, Tools & Hardware
Management System Certification:
ISO 9001, ANSI/ESD
Company Introduction:
OEM ODM Made in China!
JETYOO LIMITED PROFILES
JETYOO founded in 2000, focuses on instruments, equipments and all kinds of accessories, consumables. We strive to provide excellent one-stop, customized component shopping solutions including design, manufacturing, procurement and door to door logistics to our clients. JETYOO is based upon Asian resources and has extensive industrial experience, professional technical ability and providing high quality, considerate services to clients from the globe.
More than 20 years, JETYOO has won recognition and trust from our customers around the world, particularly from Europe and USA by our professional services and effective price. JETYOO has adhered to the idea of "Ingenuity wins customers, Professional creates values" from the very beginning. We strive to contribute "Made in China" with the image of high-quality and let our clients to see the spirit of ingenuity in China.
We will continue to make full use of ourselves resource advantages to provide a good platform for international economic, trade and cultural exchanges, to achieve win-win development, and strive to make a blueprint for the economic and trade development between China and countries along the Belt and Road route.
We are now looking clients all over the world, we would like to invite you to cooperate with us to build up a long-term cooperation relationship.
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